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1/24 october 2004 vn800s-e VN800PT-E high side driver rev. 1 table 1. general features cmos compatible input thermal shutdown current limitation shorted load protection undervoltage and overvoltage shutdown protection against loss of ground very low stand-by current reverse battery protection (*) in compliance with the 2002/95/ec european directive description the vn800s-e, VN800PT-E are monolithic devices made by using stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes. figure 1. package active current limitation combined with thermal shutdown and automatic restart protect the device against overload. device automatically turns off in case of ground pin disconnection. this device is especially suitable for industrial applications in norms conformity with iec1131 (programmable controllers international standard). table 2. order codes note: (*) see application schematic at page 10. type r ds(on) i out v cc vn800s-e VN800PT-E 135 m ? 0.7 a 36 v so-8 ppak package tube tape and reel so-8 vn800s-e vn800str-e ppak VN800PT-E vn800pttr-e
vn800s-e / VN800PT-E 2/24 figure 2. block diagram table 3. absolute maximum ratings symbol parameter value unit so-8 ppak v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/- 10 ma v in input voltage range -3/+v cc v v stat dc status voltage + v cc v v esd electrostatic discharge (human body model: r=1.5k ? ; c=100pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v p tot power dissipation t c =25c 4.2 41.7 w e max maximum switching energy (l=77.5mh; r l =0 ? ; v bat =13.5v; t jstart =150oc; i l =1.5a) 121 mj e max maximum switching energy (l=125mh; r l =0 ? ; v bat =13.5v; t jstart =150oc; i l =1.5a) 195 mj t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c l max max inductive load (v cc =30v; i load =0.5a; t amb =100c; rth case>ambient 25c/w) 2h undervoltage overtemperature gnd input output overvoltage current limiter logic driver power clamp status v cc clamp detection detection detection v cc
3/24 vn800s-e / VN800PT-E figure 3. configuration diagram (top view) & suggested connections for unused and n.c. pins figure 4. current and voltage conventions table 4. thermal data ( 1 ) when mounted on fr4 printed circuit board with 0.5 cm 2 of copper area (at least 35 thick) connected to all v cc pins. ( 2 ) when mounted on fr4 printed circuit board with 2 cm 2 of copper area (at least 35 thick). ( 3 ) when mounted on fr4 printed circuit board with 0.5 cm 2 of copper area (at least 35 thick) connected to all v cc pins. ( 4 ) when mounted on fr4 printed circuit board with 6 cm 2 of copper area (at least 35 thick). symbol parameter value unit so-8 ppak r thj-case thermal resistance junction-case max -3c/w r thj-lead thermal resistance junction-lead max 30 - c/w r thj-amb thermal resistance junction-ambient max max 93 ( 1 ) 78 ( 3 )c/w 82 ( 2 ) 45 ( 4 )c/w connection / pin status n.c. output input floating x x x x to ground x through 10k ? resistor v cc v cc output output n.c. gnd status input 1 4 5 8 5 4 3 2 1 status output gnd input v cc so-8 ppak input i s i in v in v cc status i stat v stat gnd v cc i out v out i gnd output v f
vn800s-e / VN800PT-E 4/24 electrical characteristics (8v 5/24 vn800s-e / VN800PT-E electrical characteristics (continued) table 8. v cc - output diode table 9. status pin table 10. protections (see note 1) note: 1. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic sign als must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. figure 5. symbol parameter test conditions min. typ. max. unit v f forward on voltage -i out =0.6a; t j =150c 0.6 v symbol parameter test conditions min typ max unit v stat status low output voltage i stat =1.6 ma 0.5 v i lstat status leakage current normal operation; v stat =v cc =36 v 10 a c stat status pin input capacitance normal operation; v stat = 5v 30 pf symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload condition t j >t jsh 20 s i lim dc short circuit current v cc =24v; r load =10m ? 0.7 2 a v demag turn-off output clamp voltage i out =0.5 a; l=6mh v cc -47 v cc -52 v cc -57 v overtemp status timing t j >t jsh v in v stat t sdl t sdl
vn800s-e / VN800PT-E 6/24 table 11. truth table figure 6. switching time waveforms conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) t d(off) t d(on) v in t t 90%
7/24 vn800s-e / VN800PT-E table 12. electrical transient requirements on v cc pin figure 7. peak short circuit current test circuit iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 ? 2 +25 v +50 v +75 v +100 v 0.2 ms 10 ? 3a -25 v -50 v -100 v -150 v 0.1 s 50 ? 3b +25 v +50 v +75 v +100 v 0.1 s 50 ? 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 ? 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 ? iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5ceee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 10k ? control unit r in input gnd output r l =10m ? + v cc gnd status v cc
vn800s-e / VN800PT-E 8/24 figure 8. avalanche energy test circuit 10k ? control unit r in input gnd output load + v cc gnd status v cc
9/24 vn800s-e / VN800PT-E figure 9. waveforms status input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc v cc >v ov status input status undefined load voltage v cc vn800s-e / VN800PT-E 10/24 figure 10. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device?s datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k ?) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of c i/os. -v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 20ma; v oh c 4.5v 5k ? r prot 65k ? . recommended r prot value is 10k ?. v cc inputn gnd statusn outputn volt. reg bus asic control & diagnostic i/o 5v 24vdc v cc dgnd vgnd rgnd rprot rprot load r l
11/24 vn800s-e / VN800PT-E figure 11. off state output current figure 12. high level input current figure 13. status leakage current figure 14. on state resistance vs t case figure 15. on state resistance vs v cc figure 16. input high level -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 il(off1) (a) off state vcc=36v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 1 2 3 4 5 6 7 8 iih (a) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 ilstat (a) vstat=vcc=36v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 50 100 150 200 250 300 350 400 ron (mohm) iout=0.5a vcc=8v; 13v; 36v 5 10152025303540 vcc (v) 0 50 100 150 200 250 300 350 400 ron (mohm) iout=0.5a tc= - 40oc tc= 25oc tc= 150oc -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v)
vn800s-e / VN800PT-E 12/24 figure 17. input low level figure 18. turn-on voltage slope figure 19. overvoltage shutdown figure 20. input hysteresis voltage figure 21. turn-off voltage slope figure 22. i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 200 400 600 800 1000 1200 1400 1600 dvout/dt(on) (v/ms) vcc=24v rl=48ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 100 200 300 400 500 600 700 800 dvout/dt(off) (v/ms) vcc=24v rl=48ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 ilim (a) vcc=24v rl=10mohm
13/24 vn800s-e / VN800PT-E figure 23. so-8 maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 ? in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. 0.1 1 10 1 10 100 1000 l(mh) i lmax (a) a b c v in , i l t demagnetization demagnetization demagnetization
vn800s-e / VN800PT-E 14/24 figure 24. ppak maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 ? in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. 0.1 1 10 1 10 100 1000 l(mh) i lmax (a) a b c v in , i l t demagnetization demagnetization demagnetization
15/24 vn800s-e / VN800PT-E so-8 thermal data figure 25. so-8 pc board figure 26. so-8 r thj-amb vs pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m, copper areas: 0.14cm 2 , 2cm 2 ). 70 75 80 85 90 95 100 105 110 00.511.522.5 pcb cu heatsink area (cm^2) rthj_amb (oc/w) so8 at 2 pins connected to tab
vn800s-e / VN800PT-E 16/24 ppak thermal data figure 27. ppak pc board figure 28. ppak r thj-amb vs pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 60mm x 60mm, pcb thickness=2mm, cu thickness=35 m, copper areas: 0.44cm 2 , 8cm 2 ). 0 10 20 30 40 50 60 70 80 90 0246810 pcb cu heatsink area (cm^2) rthj_amb (oc/w)
17/24 vn800s-e / VN800PT-E figure 29. so-8 thermal impedance junction ambient single pulse figure 30. thermal fitting model of a single channel hsd in so-8 pulse calculation formula table 13. thermal parameter 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) 0.5 cm 2 2 cm 2 t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj area/island (cm 2 )0.142 r1 (c/w) 0.24 r2 (c/w) 1.2 r3 ( c/w) 4.5 r4 (c/w) 21 r5 (c/w) 16 r6 (c/w) 58 28 c1 (w.s/c) 0.00015 c2 (w.s/c) 0.0005 c3 (w.s/c) 7.50e-03 c4 (w.s/c) 0.045 c5 (w.s/c) 0.35 c6 (w.s/c) 1.05 2 z th r th z thtp 1 ? () + ? = where t p t ? =
vn800s-e / VN800PT-E 18/24 figure 31. ppak thermal impedance junction ambient single pulse figure 32. thermal fitting model of a single channel hsd in ppak pulse calculation formula table 14. thermal parameter 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) 0.44 cm 2 6 cm 2 t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj area/island (cm 2 )0.446 r1 (c/w) 0.04 r2 (c/w) 0.25 r3 ( c/w) 0.3 r4 (c/w) 2 r5 (c/w) 15 r6 (c/w) 61 24 c1 (w.s/c) 0.0008 c2 (w.s/c) 0.007 c3 (w.s/c) 0.02 c4 (w.s/c) 0.3 c5 (w.s/c) 0.45 c6 (w.s/c) 0.8 5 z th r th z thtp 1 ? () + ? = where t p t ? =
19/24 vn800s-e / VN800PT-E package mechanical table 15. so-8 mechanical data figure 33. so-8 package dimensions symbol millimeters min typ max a 1.75 a1 0.1 0.25 a2 1.65 a3 0.65 0.85 b 0.35 0.48 b1 0.19 0.25 c 0.25 0.5 c1 45 (typ.) d4.8 5 e5.8 6.2 e1.27 e3 3.81 f3.8 4 l 0.4 1.27 m 0.6 s 8 (max.) l1 0.8 1.2
vn800s-e / VN800PT-E 20/24 package mechanical table 16. ppak mechanical data figure 34. ppak package dimensions symbol millimeters min typ max a 2.20 2.40 a1 0.90 1.10 a2 0.03 0.23 b 0.40 0.60 b2 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 d1 5.1 d 6.00 6.20 e 6.40 6.60 e1 4.7 e1.27 g 4.90 5.25 g1 2.38 2.70 h 9.35 10.10 l2 0.8 1.00 l4 0.60 1.00 r0.2 v2 0o 8o package weight gr. 0.3 p032t1
21/24 vn800s-e / VN800PT-E figure 35. so-8 tube shipment (no suffix) figure 36. so-8 tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a 3.2 b 6 c ( 0.1) 0.6 c b a tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions all dimensions are in mm. base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4
vn800s-e / VN800PT-E 22/24 figure 37. p pak suggested pad layout and tube shipment (no suffix) figure 38. p pak tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 75 bulk q.ty 3000 tube length ( 0.5) 532 a 6 b 21.3 c ( 0.1) 0.6 a c b 6.7 1.8 3 reel dimensions all dimensions are in mm. base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 2.75 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
23/24 vn800s-e / VN800PT-E revision history table 17. revision history date revision description of changes oct. -2004 1 - first issue
vn800s-e / VN800PT-E 24/24 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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